System-on-Chip Test Architectures
Nanometer Design for Testability
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System-on-Chip Test Architectures by Laung-Terng Wang
Book DescriptionModern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
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Book DetailsISBN: 9780123739735
(235mm x 190mm x 41mm)
Imprint: Morgan Kaufmann Publishers In
Publisher: Elsevier Science & Technology
Publish Date: 8-Jan-2008
Country of Publication: United States
Books By Author Laung-Terng Wang
Electronic Design Automation, Hardback (March 2009)
Covers the spectrum of the Electronic Design Automation (EDA) flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test. This book contains the advancements, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks.
VLSI Test Principles and Architectures, Hardback (August 2006)» View all books by Laung-Terng Wang
A comprehensive guide to DFT methods that shows the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. It provides coverage of design for testability. It presents coverage of industry practices commonly found in commercial DFT tools.
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Author Biography - Laung-Terng Wang
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
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