VLSI Test Principles and Architectures
Design for Testability
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VLSI Test Principles and Architectures by Laung-Terng Wang
Book DescriptionThis book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
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Book DetailsISBN: 9780123705976
(235mm x 191mm x 52mm)
Imprint: Morgan Kaufmann Publishers In
Publisher: Elsevier Science & Technology
Publish Date: 14-Aug-2006
Country of Publication: United States
Books By Author Laung-Terng Wang
Electronic Design Automation, Hardback (March 2009)
Covers the spectrum of the Electronic Design Automation (EDA) flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test. This book contains the advancements, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks.
System-on-Chip Test Architectures, Hardback (January 2008)» View all books by Laung-Terng Wang
A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.
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Author Biography - Laung-Terng Wang
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
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